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FPGA-розробник
Місто:
Київ
Контактна інформація
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Kucherenko Oleg
FPGA engineer / Hardware engineer
[відкрити контакти ](див. вище в блоці «контактна інформація») [відкрити контакти ](див. вище в блоці «контактна інформація») Kyiv, Ukraine
Projects
Super compact fanless x86 embedded PCs
2023-2024
4x4” single board PCs → Aluminum encloser vs IP67/IK10 protection rates
• Mechanical and thermal design of final product using 4x4” Intel NUC single board PCs, copper heat pipes, bulk copper heat exchangers.
• Achieved stable 100% fanless operation of Intel Celeron 12th gen. (low-cost option) and Intel i5 13th gen. (high performance option) boards in indoor and outdoor scenarios at final PCs dimensions only about 110 x 130 x 40mm.
Ultra low light analog mini camera for FPV drones
2022-2023
0.5-1.3 Mp image sensor → FPGA vs SRAM → CVBS video encoder
• Developed camera board “from A to Z”: custom image processing algorithms, component selection, noise-aware schematic and PCB design.
• Developed FW for Intel MAX10 FPGA: interfaces image sensor ↔ FPGA, FPGA → video encoder : I²C, SERDES; real-time image processing pipelines:
Bayer → RGB/YUV, dark frame subtraction, noise reduction, HDR, detail enhancement, multi-exposure fusion.
• Used design software: Intel Quartus Prime, Altium Designer, Matlab/Simulink (at the algorithms development stage).
• Low level RTL design: schematic + VHDL.
• Achieved superior light sensitivity and low noise level.
GigE machine vision camera for ITS application
2019-2021
2-8 Mp global shutter image sensor → FPGA vs DDR RAM → GigE output
• Developed part of FW for Xilinx Spartan 7 FPGA for real-time image processing pipelines (gain/offset correction, noise reduction, HDR, detail enhancement, multi-exposure fusion) and synchronization of Global Shutter Image Sensor vs NIR LED lights in different impulse modes.
• Collaborated with FW developer of GigE interface and SW developer of final embedded PC-based ITS system to optimize architecture and performance.
• Used design software: Xilinx Vivado IDE.
• Low level RTL design: schematic + Verilog HDL.
• Achieved stable car shape and license plate acquisition for vehicles speed up to 270km/h suitable for next stage SW recognition of model/license plate.
Automotive 360° Surround view and video recording system
2016-2018
8x CVBS inputs / 2x MIPI CSI video inputs → SoC vs DDR RAM → video outputs
• Led a team of HW engineers to design main system board with target specifications and cost optimization.
• Developed part of FW for Xilinx Zynq 7000 SoC: video acquisition from CVBS and MIPI CSI video inputs, CVBS and HDMI video outputs, on-board image processing pipelines: synchronization, up/downscaling, bird view calibration and stitching, motion detection.
• Collaborated with developer of embedded FW for ARM CPU of Zynq SoC to design and optimize final surround view and video recording system architecture and performance.
• Used design software: Xilinx Vivado IDE, Altium Designer.
• Low level RTL design: schematic + Verilog HDL.
Education
• Master of Science in Electronics.
NTUU «Кyiv PoIytechnic Institute», Faculty of Electronics, Department of Electronic devices and systems.
September 1996 – July 2002.
Skills
• Analog, digital and mixed signal systems design.
• High speed multilayer PCB design.
• Low power/low area CPLD design.
• High performance FPGA design: high speed interfaces/controllers, digital signal and image processing.
• RTL design entry: VHDL, Verilog, Schematic.
Experienced with
• Altera/Intel FPGAs and CPLDs:
FPGAs: ACEX, Cyclone III/V, MAX 10;
CPLDs: MAX 3000A.
• Xilinx/AMD FPGAs and SoCs:
FPGAS: Spartan 7; SoCs: Zynq 7000.
Design software
• Altera Max+Plus II, Altera Quartus Prime, Xilinx Vivado IDE, Modelsim.
• Altium Designer.
• MatLab/Simulink.
Experienced in design
• Interfaces: ADC/DAC ↔ FPGA, FPGA↔MCU, Image Sensor↔FPGA.
• Controllers: DDR RAM, Async SRAM, Sync SRAM, NAND, I²C, SPI, MIPI CSI.
• High speed buses: PCI Target 33MHz, PCI Master/Target 66MHz, PCI-Express.
• Real-time signal and image processing pipelines: signal/image denoising and reconstruction, dynamic range enhancement, signals/images fusion.
• Sensor Array processing.
Languages
• Ukrainian, Russian, English (Upper Int.)
Multi-channel CVBS Video capture boards (PCI/PCIe >10 models)
2005-2015
4-64 input video channels / 6-12 audio channels / 16 GPIOs → FPGA vs MCU
• Led a team of HW engineers to achieve target BOM cost and performance for full range of video capture boards (PCI, PCIe x1, PCIe x4, mini PCI).
• Developed FW for Altera Cyclone III FPGA: PCI 33Mhz Master/Target IP core, PCI 66Mhz Master/Target IP core, I²C bus controller IP core, on-board image processing pipelines (downscaling, image enhancement, motion detection with parameters defined from high level software).
• Collaborated with team of SW developers to design and optimize performance of final PC-based CCTV system - Spotter™.
• Used design software: Altera Quartus II, Modelsim.
• Low level RTL design: schematic + VHDL.
Board for display BIOS diagnostic codes (PCI Post Card)
2003-2004
Error code sending via PCI bus → CPLD vs PCI core → 7-segment display
• Developed board “from A to Z”: Schematic, component selection, PCB design.
• Developed firmware for Altera MAX3000 CPLD: extreme low area PCI bus 33Mhz Target IP core, suitable to fit in MAX3032 CPLD (32 macrocells).
• Used design software: Altera Quartus II, PCAD 2000.
• Low level RTL design: VHDL.
Videoprocessor for capture and processing of Analog HDTV signals from X-Ray industrial and medical CCTV systems (1)
2001-2002
HDTV 1249i → 60MHz ADC → FPGA vs PCI core vs SDRAM → 60MHz DAC
• Developed board “from A to Z”: Schematic, component selection, high speed PCB design (analog and digital areas, high speed ADC and DAC, up to 60MHz video buses, up to 66MHz PCI bus).
• Developed FW for Altera ACEX FPGA: “live” video capture and/or display, PCI 32bit/66Mhz Master/Target bus controller, on-board image processing pipelines: noise reduction, dynamic range and details enhancement (3).
• Collaborated with Software developer to design common PC-based video capture/processing/storage system - Direcon D01 (5).
• Used design software: Altera Quartus II, PCAD 2000.
• Low level RTL design: schematic + VHDL.
Video Upconverter board CGA/EGA → SVGA 100Hz (2)
2000-2001
20MHz ADCx3 (R, G, B) → CPLD vs x2 SRAM banks → 100MHz DAC 3x
• Developed board “from A to Z”: Schematic, component selection, high speed PCB design (analog and digital areas, ADCs/DAC, up to 100MHz video buses), firmware for Altera MAX 3000A CPLDs.
• Used design software: Altera Max+Plus II, PCAD 2000.
• Low level RTL design: schematic + Altera HDL.
Articles
[1] A.V. Terletsky, O.I. Kucherenko, A.S. Podoselnic. (Electronics and communications, №13).
Videoprocessor for recording and processing of video signals in X-Ray CCTV systems.
[2] A.V. Terletsky, O.I. Kucherenko (Electronics and communications, №14).
Application of the multiple scanning method to improve the quality of television images.
[3] A.V. Terletsky, O.I. Kucherenko, A.S. Podoselnic. (Electronics and communications, №15).
Features of displaying dynamic patches of television images in computer systems.
[4] A.V. Terletsky, A.S. Podoselnic, O.I. Kucherenko. (Electronics and communications, №16).
Study of frequency characteristics of X-ray CCTV systems.
[5] A.V. Terletskiy, A.S. Podoselnic, O.I. Kucherenko, N.G. Beluy.
(4th national scientific and technical conference/exhibition “Non-invasive control and technical diagnostics”).
PC-based system “Direcon D01” for acquisition, processing and storage of information from X-Ray video detectors.
FPGA engineer / Hardware engineer
[
Projects
Super compact fanless x86 embedded PCs
2023-2024
4x4” single board PCs → Aluminum encloser vs IP67/IK10 protection rates
• Mechanical and thermal design of final product using 4x4” Intel NUC single board PCs, copper heat pipes, bulk copper heat exchangers.
• Achieved stable 100% fanless operation of Intel Celeron 12th gen. (low-cost option) and Intel i5 13th gen. (high performance option) boards in indoor and outdoor scenarios at final PCs dimensions only about 110 x 130 x 40mm.
Ultra low light analog mini camera for FPV drones
2022-2023
0.5-1.3 Mp image sensor → FPGA vs SRAM → CVBS video encoder
• Developed camera board “from A to Z”: custom image processing algorithms, component selection, noise-aware schematic and PCB design.
• Developed FW for Intel MAX10 FPGA: interfaces image sensor ↔ FPGA, FPGA → video encoder : I²C, SERDES; real-time image processing pipelines:
Bayer → RGB/YUV, dark frame subtraction, noise reduction, HDR, detail enhancement, multi-exposure fusion.
• Used design software: Intel Quartus Prime, Altium Designer, Matlab/Simulink (at the algorithms development stage).
• Low level RTL design: schematic + VHDL.
• Achieved superior light sensitivity and low noise level.
GigE machine vision camera for ITS application
2019-2021
2-8 Mp global shutter image sensor → FPGA vs DDR RAM → GigE output
• Developed part of FW for Xilinx Spartan 7 FPGA for real-time image processing pipelines (gain/offset correction, noise reduction, HDR, detail enhancement, multi-exposure fusion) and synchronization of Global Shutter Image Sensor vs NIR LED lights in different impulse modes.
• Collaborated with FW developer of GigE interface and SW developer of final embedded PC-based ITS system to optimize architecture and performance.
• Used design software: Xilinx Vivado IDE.
• Low level RTL design: schematic + Verilog HDL.
• Achieved stable car shape and license plate acquisition for vehicles speed up to 270km/h suitable for next stage SW recognition of model/license plate.
Automotive 360° Surround view and video recording system
2016-2018
8x CVBS inputs / 2x MIPI CSI video inputs → SoC vs DDR RAM → video outputs
• Led a team of HW engineers to design main system board with target specifications and cost optimization.
• Developed part of FW for Xilinx Zynq 7000 SoC: video acquisition from CVBS and MIPI CSI video inputs, CVBS and HDMI video outputs, on-board image processing pipelines: synchronization, up/downscaling, bird view calibration and stitching, motion detection.
• Collaborated with developer of embedded FW for ARM CPU of Zynq SoC to design and optimize final surround view and video recording system architecture and performance.
• Used design software: Xilinx Vivado IDE, Altium Designer.
• Low level RTL design: schematic + Verilog HDL.
Education
• Master of Science in Electronics.
NTUU «Кyiv PoIytechnic Institute», Faculty of Electronics, Department of Electronic devices and systems.
September 1996 – July 2002.
Skills
• Analog, digital and mixed signal systems design.
• High speed multilayer PCB design.
• Low power/low area CPLD design.
• High performance FPGA design: high speed interfaces/controllers, digital signal and image processing.
• RTL design entry: VHDL, Verilog, Schematic.
Experienced with
• Altera/Intel FPGAs and CPLDs:
FPGAs: ACEX, Cyclone III/V, MAX 10;
CPLDs: MAX 3000A.
• Xilinx/AMD FPGAs and SoCs:
FPGAS: Spartan 7; SoCs: Zynq 7000.
Design software
• Altera Max+Plus II, Altera Quartus Prime, Xilinx Vivado IDE, Modelsim.
• Altium Designer.
• MatLab/Simulink.
Experienced in design
• Interfaces: ADC/DAC ↔ FPGA, FPGA↔MCU, Image Sensor↔FPGA.
• Controllers: DDR RAM, Async SRAM, Sync SRAM, NAND, I²C, SPI, MIPI CSI.
• High speed buses: PCI Target 33MHz, PCI Master/Target 66MHz, PCI-Express.
• Real-time signal and image processing pipelines: signal/image denoising and reconstruction, dynamic range enhancement, signals/images fusion.
• Sensor Array processing.
Languages
• Ukrainian, Russian, English (Upper Int.)
Multi-channel CVBS Video capture boards (PCI/PCIe >10 models)
2005-2015
4-64 input video channels / 6-12 audio channels / 16 GPIOs → FPGA vs MCU
• Led a team of HW engineers to achieve target BOM cost and performance for full range of video capture boards (PCI, PCIe x1, PCIe x4, mini PCI).
• Developed FW for Altera Cyclone III FPGA: PCI 33Mhz Master/Target IP core, PCI 66Mhz Master/Target IP core, I²C bus controller IP core, on-board image processing pipelines (downscaling, image enhancement, motion detection with parameters defined from high level software).
• Collaborated with team of SW developers to design and optimize performance of final PC-based CCTV system - Spotter™.
• Used design software: Altera Quartus II, Modelsim.
• Low level RTL design: schematic + VHDL.
Board for display BIOS diagnostic codes (PCI Post Card)
2003-2004
Error code sending via PCI bus → CPLD vs PCI core → 7-segment display
• Developed board “from A to Z”: Schematic, component selection, PCB design.
• Developed firmware for Altera MAX3000 CPLD: extreme low area PCI bus 33Mhz Target IP core, suitable to fit in MAX3032 CPLD (32 macrocells).
• Used design software: Altera Quartus II, PCAD 2000.
• Low level RTL design: VHDL.
Videoprocessor for capture and processing of Analog HDTV signals from X-Ray industrial and medical CCTV systems (1)
2001-2002
HDTV 1249i → 60MHz ADC → FPGA vs PCI core vs SDRAM → 60MHz DAC
• Developed board “from A to Z”: Schematic, component selection, high speed PCB design (analog and digital areas, high speed ADC and DAC, up to 60MHz video buses, up to 66MHz PCI bus).
• Developed FW for Altera ACEX FPGA: “live” video capture and/or display, PCI 32bit/66Mhz Master/Target bus controller, on-board image processing pipelines: noise reduction, dynamic range and details enhancement (3).
• Collaborated with Software developer to design common PC-based video capture/processing/storage system - Direcon D01 (5).
• Used design software: Altera Quartus II, PCAD 2000.
• Low level RTL design: schematic + VHDL.
Video Upconverter board CGA/EGA → SVGA 100Hz (2)
2000-2001
20MHz ADCx3 (R, G, B) → CPLD vs x2 SRAM banks → 100MHz DAC 3x
• Developed board “from A to Z”: Schematic, component selection, high speed PCB design (analog and digital areas, ADCs/DAC, up to 100MHz video buses), firmware for Altera MAX 3000A CPLDs.
• Used design software: Altera Max+Plus II, PCAD 2000.
• Low level RTL design: schematic + Altera HDL.
Articles
[1] A.V. Terletsky, O.I. Kucherenko, A.S. Podoselnic. (Electronics and communications, №13).
Videoprocessor for recording and processing of video signals in X-Ray CCTV systems.
[2] A.V. Terletsky, O.I. Kucherenko (Electronics and communications, №14).
Application of the multiple scanning method to improve the quality of television images.
[3] A.V. Terletsky, O.I. Kucherenko, A.S. Podoselnic. (Electronics and communications, №15).
Features of displaying dynamic patches of television images in computer systems.
[4] A.V. Terletsky, A.S. Podoselnic, O.I. Kucherenko. (Electronics and communications, №16).
Study of frequency characteristics of X-ray CCTV systems.
[5] A.V. Terletskiy, A.S. Podoselnic, O.I. Kucherenko, N.G. Beluy.
(4th national scientific and technical conference/exhibition “Non-invasive control and technical diagnostics”).
PC-based system “Direcon D01” for acquisition, processing and storage of information from X-Ray video detectors.
Резюме кандидата розміщено за адресою: https://www.work.ua/resumes/10893770/