Особисті дані приховані

Rostyslav Melnyk
Target positions: ASIC RTL Design Engineer • FPGA Design Engineer • VLSI Design Engineer • Circuit Design Engineer • SoC Integration Engineer • CPU Design Methodology Engineer (long-term)
Education
National Technical University of Ukraine 'Igor Sikorsky Kyiv Polytechnic Institute' (KPI)
Faculty of Electronics
Bachelor's Degree in Micro- and Nanosystems Engineering
2nd Year (started September 2024)
Technical Skills
HDLs & Modeling
• SystemVerilog
• Verilog
• RTL design
• Structural and behavioral modeling
• Finite State Machines (Moore & Mealy)
Digital Logic
• Combinational and sequential logic
• Multiplexers
• Decoders
• Priority encoders
• Registers & Flip-Flops
• Full Adder
• Tri-state buffers
• Seven-segment decoder
Verification & Analysis
• Testbench development
• Self-checking testbenches
• Functional verification
• VCD waveform analysis
EDA Tools
• Verilator
• Yosys
• Netlistsvg
• Surfer
• GTKWave
• LTspice
• EveryCircuit
Programming
• C (basic)
• Python (basic)
• Git
• VS Code
• macOS/Linux Terminal
Hardware Fundamentals
• Digital Electronics
• CMOS Logic
• MOSFET Fundamentals
Projects
• CMOS Logic Design & Simulation: Designed and simulated CMOS logic circuits in EveryCircuit (AND, OR, NOR, XOR, Majority, Minority, Transmission Gates).
• SystemVerilog RTL Design: Implemented multiplexers (2:1, 4:1, hierarchical), priority encoders, decoders, registers, flip-flops, seven-segment decoder, and Moore/Mealy finite-state machines.
• Verification & Timing Analysis: Developed self-checking testbenches, generated VCD waveforms, and analyzed timing using Surfer.
• RTL Synthesis & Visualization: Synthesized RTL designs with Yosys and generated gate-level schematics using Netlistsvg.
• Workflow Automation: Created shell scripts to automate Verilator simulation and schematic generation.
GitHub
GitHub: https://github.com/rostyslavmelnyk33 (username: rostyslavmelnyk33)
Languages
Ukrainian — Native
English — B1 (improving)